In SR Latch, there is a strange input condition S=1 and R = 1. When both are asserted both Q and Qbar(Qinv) are 1. To avoid this ambiguity, D Latch which is also called as Data Latch has come up with a solution by connecting R input with inverted output of S pin in SR Latch.
This circuit avoid that strange input condition of SR Latch.
D Latch with Enable:
In D Latch with enable circuit, D input controls what the next state should be and the enable input CLK controls when the state should change.
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D Latch with Enable pin CLK |
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| Truth Table |
Enable CLK controls the flow of the data through the SR Latch. When CLK = 1 the latch is transparent and data flows through the latch. When CLK = 0 the latch is opaque and data flow is blocked and Q retains its previous state or value. Because of this D Latch is also called as transparent latch or a level sensitive latch.